John G. Webster (Editor) 's 64.VLSI Systems PDF

By John G. Webster (Editor)

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The registers Rin and Rout symbolize off-chip registers and are controlled by the off-chip clock source, which also provides the on-chip clock signals, because the circuit is assumed to be a fully synchronous system. This relationship is represented by TSkewin,out = TSkewin,i + TSkewi, j + · · · + TSkewl,out = 0 (15) Therefore, to satisfy Eq. (15), in Fig. 20, ⌬1 ϭ ⌬2 ϭ ⌬. Although it is possible to have off-chip nonzero clock skew, it is desirable to ensure that the clock skew between VLSI input/output (I/O) approaches zero, in order to avoid complicating the design of a circuit board or the specification of the interface of the circuit with other components also controlled by the same clock source.

29, 30, 36, 130–138, and is described in this section. Starting with the timing characteristics of the circuit, such as the minimum and maximum delay of each combinational logic block and register, it is possible to obtain the localized clock skews and the minimum clock period. This information is determined by formulating the optimal clock scheduling problem as a linear programming problem and solving with linear programming techniques (36,134). The concept of scheduling the system-wide clock skews for improved performance while minimizing the likelihood of race conditions was first presented by Fishburn in 1990 (36), although the application of localized clock skew to increase the clock frequency and to eliminate race conditions was known previously (34).

5) must be satisfied. To avoid race conditions between two sequentially adjacent registers, Ri and Rj, Eq. (6) must be satisfied. The system-wide clock period is minimized by finding a set of clock skew values that satisfy Eqs. (5) and (6) for each local data path and Eq. (15) for each global data path. These relationships are sufficient conditions to determine the optimal clock skew schedule such that the overall circuit performance is maximized while eliminating any race conditions. The timing characteristics of each local data path are assumed to be known.

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64.VLSI Systems by John G. Webster (Editor)


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